As commercial storage becomes increasingly expensive, more and more of the Education vertical is looking at Open Source solutions for storage. In this article, we discuss the value of OpenZFS for Universities and how system administrators can best leverage it to their benefit.
RISC-V: The New Architecture on the Block
RISC-V: The New Architecture on the Block
The majority of people in the tech community are well aware of the two main chip architectures: x86 and ARM. Each has its own strengths and weaknesses. Today, however, we’re talking about the new kid on the block: RISC-V. Today, we will look at the history of RISC-V and how it differs from the other offerings.
Where did RISC-V Come from?
Just like BSD, the RISC-V architecture was forged in the academic fires of the University of California, Berkeley. Professor Krste Asanović was working at the “Parallel Computing Laboratory (Par Lab) at UC Berkeley” in 2010. At the time, Asanović’s project needed an open-source computer system. He looked at what was available and decided to create something new. He figured that it would be a “short, three-month project over the summer”. He started working on the project in May 2010 and was joined by two of his graduate students, Yunsup Lee and Andrew Waterman. Later, David Patterson joined the project. Patterson originally coined the term RISC and contributed to a lot of RISC development. (RISC-V’s name is a reference to the fact that it was the fifth RISC project he worked on).
In a short paper entitled Instructions Sets Should be Free: The Case for RISC-V, Asanović outlines why he thought it was necessary to create a new Instruction Set Architecture or ISA. He said that having a “viable freely open ISA” would “enable a real free open market of processor designs, which patents on ISA quirks prevent”. An open-source ISA would lead to “greater innovation via free-market competition”, shorter time to market due to “shared open core designs” and “processors becoming affordable for more devices”. He noted that other options had strings attached which made them hard for university researchers to use.
The RISC-V specifications were published in 2011 and put in the public domain. Later, the “actual tech report text (an expression of the specification)” was released under a Creative Commons license to allow improvements. The RISC-V Foundation was created in 2015 to “build an open, collaborative community of software and hardware innovators based on the RISC-V ISA”.
Three years later, the RISC-V Foundation announced a collaboration with the Linux Foundation, where the latter would provide “member management, accounting, training programs, infrastructure tools, community outreach, marketing, legal, and other open-source services and expertise”. The same year, the RISC-V Foundation moved to Switzerland to avoid potential conflicts with US laws and became RISC-V International.
How is RISC-V Different from the Alternatives?
One of the biggest differences between RISC-V and its alternatives is the licensing they use. The x86 architecture has very limited licensing. It was developed by Intel and for many years it was only made by them. According to Forbes, x86 is also licensed by “AMD at the behest of the courts and U.S. government for an alternative source and to some Chinese vendors for use with Intel designed hardware processing blocks that cannot be modified”.
On the other hand, ARM licenses are more widely available. ARM Limited develops the CPU designs and licenses them to chipmakers. “ARM licenses its designs to third-party designers, like Qualcomm and Samsung, which then add their own enhancements…this also often requires licensors to sign non-disclosure agreements designed to keep aspects of a chip’s design private. That’s hardly surprising, considering its entire business model isn’t shaped around manufacturing, but rather, intellectual property.” That’s why there are so many cheap Raspberry Pi alternatives available on the web.
RISC-V is free from the limitation of licensing. “Anyone can use the ISA without any license or royalty fees. In addition, users can easily add custom instructions for specialized functions, such as machine learning or security.” It also means that the designs can be scaled to meet different needs, from “16-bit chips for embedded systems, to 128-bit processors for supercomputers”. Currently, the 128-bit ISA is not available because it “is still in the design phase and there is only one software implementation”.
Small Number of Instructions
One of the big problems with the x86 ISA is its complexity. If you printed out the manual, it would be “~5,000 pages and that doesn’t include the extensions…Although there is no exact number, it’s estimated there are around 2,500 instructions in x86, which is just unwieldy.” On the other hand, ARMv7 “has over 600 instructions”.
Each processor has numerous transistors, and “many of these transistors represent the various instructions available”. Since RISC chips have few instructions, they need fewer transistors. Thus, chipmakers can include other things in their chips and make them smaller. “Risc-V aims to address the problem of performance by looking at ways besides shrinking the size and number of transistors.”
Up until now chipmakers have been in a race to make their transistors smaller and faster. This is because of Moore’s Law, which states that “the number of transistors that could be placed on a chip would double every two years”. Recently, it has been getting harder and harder for chip makers to shrink their deigns. RISC-V’s smaller number of instructions removes the need to.
To give you some idea of how chip design has progressed over time, let’s take a quick look at two chips 40 years apart. The first commercial microprocessor was the Intel 4004 released in 1971. It had “2,250 transistors, each measuring 10,000 nanometers (about 0.01mm)”. Now jump to 2020, when Apple released their ARM based A14 processor. That chip has 11.8 billion transistors, each measuring 5 nanometers across.
Not Affected by Prior Vulnerabilities
A press release from the RISC-V Foundation notes that “the RISC-V community has a historic opportunity to “do security right” from the get-go with the benefit of up-to-date knowledge. In particular, the open RISC-V ISA makes it possible for many different groups to experiment with alternative mitigation techniques and share results.”
RISC-V Support in FreeBSD
Even though RISC-V is relatively new and not many hardware makers support it, it has support in FreeBSD. FreeBSD divides architectures into four tiers. Tier 1 includes architectures that are fully supported by FreeBSD. These are considered “the most mature FreeBSD platforms”. Tier 2 includes architectures that aren’t as widely used, or their support is under development. They are considered “functional, but less mature FreeBSD platforms”. Tier 3 architectures are those that have only partial support in FreeBSD. “Tier 3 platforms are architectures in the early stages of development, for non-mainstream hardware platforms, or which are considered legacy systems unlikely to see broad future use.” Finally, Tier 4 platforms have no support, at all. “When a platform transitions to Tier 4, all support for the platform is removed from the source and ports trees.”
Support for RISC-V was introduced in FreeBSD 11 as a Tier-3 architecture. In FreeBSD 13, RISC-V was promoted to Tier-2. As more and more compatibly hardware becomes available, it shouldn’t be long before RISC-V reaches full support at Tier-1.
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